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What is I2C Protocol

I2C is short form of Inter Integrated Circuit.
Designed and developed by Philips in 1980 then it is adopted by lot of vendor companies.
Multi master - multi slave, means you can connect multiple ICs with the same bus.

It is serial communication protocol, provides good support to slow devices e.g. EEPROM, ADC etc.
It is 2 wire communication protocol.
In which 1 wire is for Data line/bus called as SDA and another one is for clock line/bus called as SCL.

Both the bus are bidirectional meaning master is able to send and receive the data from the slave.

Clock line is mainly controlled by master but in some scenario it can be controlled by slave also.

I2C bus speed

1) Standard mode - 100 kbps
2) Fast mode - 400 kbps
3) Fast mode Plus - 1 Mbps
4) High speed mode - 3.4 Mbps

Physical layer of the I2C protocol

I2C, learnI2C, techautotalk

All slave and master are connected with same data and clock bus.

These buses are connected to each other using the wired-AND configuration which is done by putting both pins to open drain.

The wired-AND configuration allows I2C to connect multiple nodes to the bus without any short circuit.

The open drain allows master and slave to drive the lines low and release to high impedance state.

To make the lines again high when master and slave release the bus, pullup resistors are required to pull the line High. The value of pull-up resistor is very important because the incorrect value can lead to signal loss.

How I2C communication starts

When master wants to communicate with slave, it inserts the start bit and followed by the slave address with read/write bit.

Once start bit is on the bus, all the slave will be on attentive mode.

If transmitted slave address matched with any of the slave, master will receive acknowledge bit (ACK) from the slave and then master can start the communication.

If transmitted slave address not matched with any of the slave, master will receive no acknowledge bit (NACK) from the slave.
In this case master can stop the communication by sending STOP bit or it can further try for the new  communication by sending repeated start bit.

I2C protocol - Data frame

I2C is 8 bit (1 byte) communication protocol.
In I2C, after each byte, we will get ACK or NACK bit based on slave availability.

START bit - I2C data frame

Just understand this example, you will not forget the start-stop concept for I2C.

If you want to switch-on light, you will check the current supply should be ON (Here Clock line should be High) you will press this switch to downwards means switch state (SDA data line) will be Up to Down.

The default state of SDA Data line and SCL clock line is high.
A high to low transition of the SDA line while the SCL line is high called the START condition. 

A master insert the start condition on the line to start the communication.Once start bit is inserted, I2C bus is considered as busy.

STOP bit - I2C data frame

If you want to switch-off the light, you will check the current supply should be ON (Here Clock line should be High) you will press this switch to upwards means switch state (SDA data line) will be down to up.

The default state of SCL clock line is high.

A low to high transition of the SDA line while the SCL line is high called the STOP condition.

A master insert the stop condition on the line to stop the communication.
Once stop bit is inserted, I2C bus is considered as free.

Repeated start in I2C

Stop bit terminates the communication but if master wants to start new communication before inserting stop bit, it can make use of this.

Repeated start condition is similar to start condition but both are different.
In this case master does not loose control from the bus and it can start new communication before bus goes to idle state.

Lets take an example, 
If transmitted slave address not matched with any of the slave address, master will receive NACK bit from the slave.

In this case master can stop the communication by sending STOP bit or it can further try for the new  communication by sending repeated start bit.

Byte format in I2C data frame

Every data which is transmitted over I2C bus must be 8 bit long.
I2C data bit always transmitted from MSB.

Between start and stop bits, any number of bytes can be sent and received.
but after each byte transferred, master will receive ACK and NACK bits.

Handshaking process - In I2C protocol

Acknowledge (ACK) and Not Acknowledge (NACK)

In I2C, after each byte of transfer, receiver needs to send acknowledgment.

This acknowledgement is the proof of data is received by the receiver and it wants to continue the communication.

Lets take an same data frame, master will start the communication with start condition and followed by slave address.

Here slave address will be 7 bit address and 1 bit extra for read/write bits (7+1).

After the transmission of address byte, master release the data line means SDA line in high impedance state, so that receiver (slave) will be allowed to give acknowledgement.

Which receiver will give acknowledgement? If any of the slave address is matched with transmitted address, that slave will pull down the SDA line low for the acknowledgement and after that it release the data lines.

The master generates a clock pulse to read this acknowledgment bit and continue the read or write operation.

If this transmitted address is not matched with any receiver then nobody is pull down the data lines low, master understands it is a NACK and, in that situation, master can insert a stop bit or repeated start bit for further communication.
Examples where NACK bits received by master.

When the receiver is unable to receive data, in that situation it generates a NACK bit ot stop the communication.

When the receiver is able to receive data or command but not understood by the receiver, in that situation it generates a NACK bit ot stop the communication.

If there is no device present of the same transmitted address, master will not get any acknowledge-NACK.

Clock synchronization in I2C

I2c is synchronous communication, in which clock is always generated by the master and this clock is shared by both master and slave.
In the case of multi-master, all master generate their own SCL clock, hence it is necessary that clock of all master should be synchronized. In the i2C, this clock synchronization is done by wired and logic.

For the better understanding, I am taking an example, where two masters try to communicate with a slave. In that situation, both masters generate their own clock, master M1 generate clk1 and master M2 generate clk2 and clock which observed on the bus is SCL.

The SCL clock would be the Anding (clk1 & clk2) of clk1 and clk2 and most interesting thing is that highest logic 1 of SCL line defines by the CLK which has lowest logic 1.

Arbitration in I2C

The arbitration is required in case of multi-master, where more than one master is tried to communicate with a slave simultaneously. In I2C arbitration is achieved by the SDA line.

For Example,
Suppose two masters in the I2C bus is tried to communicate with a slave simultaneously then they will assert a start condition on the bus. The SCL clock of the I2c bus would be already synchronized by the wired and logic.

In the above case, everything will be good till the state of SDA line will same what is the masters driving on the bus. If any master sees that the state of SDA line differs, what is it driving then they will exit from the communication and lose their arbitration.

Note: Master which is losing their arbitration will wait till bus become free.

Clock stretching in I2C

In I2C, slave is able to receive a byte of data on the fast rate but sometimes slave takes more time in processing the received bytes.

In that situation, slave pull down the SCL line to pause the transaction and after the processing of the received bytes, it again released the SCL line high again to resume the communication.

Means in I2c, communication can be paused by the clock stretching to holding the SCL line low and it cannot continue until the SCL line released high again.

The clock stretching is the way in which slave drive the SCL line but it is the fact, most of the slave do not drive the SCL line

Advantages of I2C communication protocol

I2C is synchronous communication protocol, so precise oscillators not required.

I2C requires only two wire, one wire for the data (SDA) and other wire for the clock (SCL).

In I2C provides the flexibility to select the transmission rate as per the requirements.

In I2C Bus, each device has unique address.

I2C supports multiple master and multiple slave.

I2C has some important features like arbitration, clock synchronization, and clock stretching.

I2C provide ACK/NACK (acknowledgment/ Not-acknowledgement) features which provide the help in error handling.

Limitation of I2C communication protocol

I2C consumes more power than other serial communication buses due to open-drain topology.

I2C is good only for the short distance.

I2C protocol has some limitation for the number of slaves, the number of the slave depends on the capacitance of the I2C bus.

It only provides few limited communication speed like 100 kbit/s,400 kbit/s etc.


I2c protocol is the easy and cheap communication protocol.

It can be multi-master or multi-slave.
In I2c we get the acknowledgment (ACK) and not acknowledgment(NACK) bits after the each transmitted byte.
But as a disadvantage with I2C is a half-duplex communication and slow as compared to SPI (serial peripheral communication).

Learn I2C protocol easily